1. Field of the Invention
The invention relates to an integrated circuit as described in the precharacterizing part of claim 1.
2. Description of Related Art
U.S. Pat. No. 5,253,137 discloses a memory with a current sense amplifier. The current sense amplifier adjusts the currents drawn from a pair of complementary bitlines so that the potential difference between the bitlines remains constantly zero. The current difference is used to generate a memory output signal. By keeping the potential difference between the bitlines constant, delays needed for charging and equalizing the bitlines are avoided.
The memory according to U.S. Pat. No. 5,253,137 has two power supply connections. Inputs of the sense amplifiers are connected to the first power supply connection via respective ones of the bit lines. The sense amplifier contains two current branches. Each input of the sense amplifier is connected to the second power supply connection via its own current branch. Each current branch contains the source/drain channel of a PMOS input transistor and a PMOS load transistor successively between the bitline and the second power supply connection. The gate of the input transistor in the each branch is cross-coupled to the drain of the input transistor in the other current branch. The gates of the load transistor are coupled to the second power supply connections.
In operation, the sense amplifier equalizes the voltage drop from the inputs of the sense amplifier to the second power supply connection, which forms a common node for the two branches. The gate/source voltage of the input transistor and the load transistor in the same current branch are substantially equal because they draw the same current. The cross-coupling ensures that the voltage drop across each current branch is the sum of the gate source voltage drops of one transistor from each branch.
This circuit has the disadvantage that it needs a power supply voltage of at least two gate/source threshold voltages to operate.